Conventional clocking disciplines of synchronous digital very-large-scale-integration (VLSI) circuits, such as single-phase positive-edge triggered clocking, entail both timing paths with a minimum and maximum delay requirement. Maximum-delay paths need to be faster than a given threshold to meet a target operating frequency while guaranteeing proper data setup timing at capturing flip-flops in pipelines, while minimum-delay paths need to be longer than a lower limit to avoid pipeline data corruption due to race through or hold time violations at the capturing flip-flop.
In particular, at the end of minimum-delay paths, pipeline data corruption may occur due to fast (e.g., faster than nominal) data path delay, long (e.g., longer than nominal) clock skew, or a degraded hold time of the capturing flip-flop. Such minimum-delay violations may be caused by integrated circuit (IC) power-supply (Vcc) noise, clock jitter, Process-Voltage-Temperature (PVT) variations, and other noise sources, and are normally aggravated by aging. In particular, clock skew typically degrades due to aging. In fact, the transistor threshold voltage (Vt) and thus the clock buffer delays may increase due to aging, especially under direct current (DC) stress found in gated clock domains, while constantly activated clock domains suffer from aging to a lesser extent.
Unfortunately, on manufactured state-of-the-art microchips, it is virtually impossible to detect and locate pipeline data corruption due to a minimum-delay problem (e.g., fast data path, increased clock skew, increased flip-flop hold time). Additionally, unlike maximum-delay problems on critical timing paths, which may be resolved by reducing the clock frequency or increasing the voltage, minimum-delay errors are not sensitive to frequency and may be impossible to eliminate with voltage adjustment. Therefore, a single minimum-delay failure could result in a completely non-functional microprocessor or system-on-chip (SoC).
The background description provided herein is for generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art or suggestions of the prior art, by inclusion in this section.